Hi,
Am 14.12.2016 um 10:28 schrieb Andreas Lausch andreas@flausch.at:
Hi,
since TrashyMG from the forums asked me to join the ML after posting this, I did.
Welcome!
https://pyra-handheld.com/boards/threads/prototype-mainboards-coming-soon.78...
So, my thoughts on that topic:
Well, we can estimate. If the core draws 5A peak current I would say the 1.25V should not change by more than 0.05V. This means < 10 mOhm. A rough estimate for standard copper traces on such PCBs is (I hope they did not make them thinner):
Copper foil thickness is defined in a build-up spec by you or the manufacturer.
What we don't know is if these Chinese do what has been agreed on :)
But I have done some measurements on a spare PCB (using a current limited power supply with 1A and a millivoltmeter). Trace resistance is in the range of 2-10mOhm (depending on what we look at).
1cm wire 100μm wide means 50 mOhm. So 500μm wide and 1cm long means 10mOhm. We might have 2cm... But all this is rough guess.
But that's just valid for DC which is not a real problem, since the DC/DC converter measures the voltage inside the SoC as far as I read.
Yes.
[Impedance calculation] It sounds like a typical service different PCBs designers would use. Not something specifically bound to a design.
It's easier to do this from source files than from gerber (because gerber does not specify the layer stack), so "good" pcb design tools integrate this to some extend
AFAIK Altium has started to have something but high end tools have it for a long time.
Well, to keep the budget low we still use EAGLE - which has no such tool integrated. Basically it is possible to export everything to another tool but it is not a standard method.
, which reduces the need for specialized tools/services. Anyway, afaik there ARE some stand-alone tools, but owners of such tools are into electronics development as well (the bad guys that want to sell you finished designs). You could maybe try to find a university that uses such tools in courses? Maybe TüV has access to such tools (because impedance calculation is also relevant for EMI)?
Well, getting access to such a tool is one side. The other is someone really working with it. It would be new for us all and we are not only financial budget limited but also time.
3rd dimension i.e. stacking them. But don't expect too much from connecting multiple capacitors in parallel. There are recommendations that a single capacitor can be better than two
Imho, the only reason that single caps are better than multiple caps is that they can be "tighter" (no copper and no casing between two caps).
Yes, that is what I also think. Adding more capacitors doesn't help much (usually - there are some exceptions).
There is of course another effect. A 10uF is "invisible" for high frequencies. So connecting a 10pF in parallel increases decoupling for very high frequencies.
Well, the story about capacitors: * digital - what is a capacitor (except a bit storage in DRAM)? * analog - capacitor removes ripple (low pass filter) and adds signal delay * RF - what is a capacitor (except an unavoidable component of a resonant circuit)?
or more in parallel. How many capacitors are used is an area of myths.
Using two caps halves the ESR, but you could as well use a bigger cap with half the ESR. The reason for 2x10µF (instead of a "better" 1x22µF with equal voltage and dielectric) is often just the availability in the recommended package.
For example: http://web.mst.edu/~jfan/slides/Archambeault1.pdf He summarizes in ~100 pages: "Value of capacitance not important"
See the forums link above.
Is it the OVERALL power consumption that causes a problem or just peaks?
The ripple caused by overall power consumption can be measured using a scope across caps.
I have done that a while ago but there was no clear result because it wasn't done systematically. Maybe I should repeat with latest knowledge about different kernel OPPs and if it depends on CPU load.
Maybe we can make the PALMAS react less aggressive, so that it doesn't increase the voltage suddenly (leading to peaks) but in lower steps?
Don't know about the exact switching frequency, but it's definitely way slower than the SoC and bulk caps should "eat" ripples at those frequencies.
ca. 1-2 MHz I think. Is certainly noted somewhere in the data sheets.
[vias]
Power planes and power traces (may) have a defined return path parallel to it, so there is not only the copper's L but also the board's C across the FR4, which defines the impedance. Vias don't have that. So, to reduce the inductance of vias by half, you just place twice as many. (Note: It's hard to route good-enough impedance-matched traces with vias without special tools (-> read docs, trial and error; been there, done that)).
And we are in the middle of that situation... No special tools but a problem.
[separate vias]
having a via per pin will move (most) of the pin's current to the "closest" via, which may or may not further reduce voltage drops.
[jtag]
It would be interesting to see what parts of the SoC are still alive to better guess the cause. But for some SoCs that may not work at all; NXP's cortex M4s may completely freeze on some hard faults, not even answering to jtag.
The last status of my test results (had to do something else for some days): * I opened two VIAs directly connected to the OMAP5 VDD-MPU on the backside of the PCB - this is almost the shortest path to the OMAP5 * I experimented with 10pF, 10nF, 10uF - even some in parallel - but could not identify any improvement, not even a slight improvement * the problem seems to appear as soon as VDD-MPU rises above ca. 1150mV and higher load - a little weaker at 1GHz and more significant >1.25GHz
So I am starting to believe that it is not decoupling of VDD-MPU but maybe too much overall GND noise (which significantly grows with voltage and CPU clock and load). Which makes the oscillator/PLL fail.
Especially as looking into the real PCB layout has shown that we have just 4 VIAs for the whole GND connection and there is room for more. So this has already been updated for the next CPU-PCB - but we don't know if it is effective until we build some (which is very very expensive - you almost get a small car for it and ED grey hair).
As a next step we have planned to remove decoupling caps from an OMAP5432EVM to see if they are really necessary for 1.5GHz operation. For that I am waiting to receive an OMAP5432EVM that is no longer needed - since if it fails it might not be possible to repair.
Best Regards Andreas Lausch a.k.a. Black Sliver
Probably the best help would be if ED can give you a prototype (as soon as the new main&display boards have been built - and if he has a spare one) so that you can do measurements and experiments in parallel to me.
BR and thanks, Nikolaus