FYI: here is a hint that something may go more wrong with 4 GB and LPAE build than with 2 GB or non-LPAE.
I don't know if this patch by itself solves all 4 GB issues or if other patches scheduled for v5.7-rc1 are needed in addition.
> Anfang der weitergeleiteten Nachricht:
>
> Von: Roger Quadros <rogerq(a)ti.com>
> Betreff: [PATCH] ARM: dts: omap5: Add bus_dma_limit for L3 bus
> Datum: 16. März 2020 um 11:27:31 MEZ
> An: <tony(a)atomide.com>
> Kopie: <hch(a)lst.de>, <robin.murphy(a)arm.com>, <robh+dt(a)kernel.org>, <nm(a)ti.com>, <t-kristo(a)ti.com>, <nsekhar(a)ti.com>, <linux-omap(a)vger.kernel.org>, <devicetree(a)vger.kernel.org>, <linux-kernel(a)vger.kernel.org>, Roger Quadros <rogerq(a)ti.com>, <stable(a)kernel.org>
>
> The L3 interconnect's memory map is from 0x0 to
> 0xffffffff. Out of this, System memory (SDRAM) can be
> accessed from 0x80000000 to 0xffffffff (2GB)
>
> OMAP5 does support 4GB of SDRAM but upper 2GB can only be
> accessed by the MPU subsystem.
>
> Add the dma-ranges property to reflect the physical address limit
> of the L3 bus.
>
> Cc: stable(a)kernel.org
> Signed-off-by: Roger Quadros <rogerq(a)ti.com>
> ---
> arch/arm/boot/dts/omap5.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
> index d0ecf54d5a23..a7562d3deb1a 100644
> --- a/arch/arm/boot/dts/omap5.dtsi
> +++ b/arch/arm/boot/dts/omap5.dtsi
> @@ -143,6 +143,7 @@
> #address-cells = <1>;
> #size-cells = <1>;
> ranges = <0 0 0 0xc0000000>;
> + dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
> ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
> reg = <0 0x44000000 0 0x2000>,
> <0 0x44800000 0 0x3000>,
> --
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>