*sigh* okay I think I need to wake up properly first...

primary SD can switch signal voltage using LDO9.

eMMC always uses 1.8V signalling and is speed-limited only by mux.

μSD cannot switch signal voltage to 1.8V hence cannot support any UHS mode.

I just noticed that your kernel called eMMC "mmc0" instead of "mmc1", that's confusing as hell. Please apply:

https://github.com/mvduin/linux/tree/patch/of-alias

On 26 March 2017 at 18:51, H. Nikolaus Schaller <hns@goldelico.com> wrote:

clock: 142000000 Hz
timing spec: 9 (mmc HS200)

Keep in mind that just because overclocking is successful in one instance doesn't mean it will work on the next board.

The strange thing is that increasing the max-frequency by 50% gives double
speed...

I think 92 MHz gets rounded down to 48 MHz and 144 MHz gets rounded down to 96 MHz.

On 27 March 2017 at 01:25, Michael Mrozek <EvilDragon@openpandora.org> wrote:

If I understood correctly, the MUX doesn't support more than 120MHz (or
60MHz, depending whether you run in SDR or DDR)

It doesn't support more than 60 MHz SDR (60 Mbit/s per IO) or 60 MHz DDR (120 Mbit/s per IO) due to max clock frequency. When using 8 data IO lines there's also the skew issue which will limit the speed to an unknown value (probably lower for writes than for reads).