Am 17.10.2018 um 07:16 schrieb H. Nikolaus Schaller <hns@goldelico.com>:

Am 17.10.2018 um 07:13 schrieb Tony Lindgren <tony@atomide.com>:

* H. Nikolaus Schaller <hns@goldelico.com> [181017 04:42]:
Am 17.10.2018 um 01:03 schrieb Tony Lindgren <tony@atomide.com>:
Well looking at the Pyra schematics to me it seems that for example
on emif1 cke0 and cke1 are both connected to U3401 and U3402. To me
it seems U3401 should only have cke0 and U3402 should have only cke1
(or the other way around) just as in "EMIF DDR3 Generic Configuration".
And the same for the other used lines, and for emif2.
Are you sure with oyur idea?
No :)

U3401 is for 16 bits and U3402 for the other 16 bits of the 32 bit EMIF channel.

Both, U3401 and U3402 have two dies inside where one responds to ODT/CKE/NCS0
and the other to ODT/CKE/NCS1. So U3401 combines what is shown as "Die 1" and "Die 2"
in the figure and U3402 combines "Die 3" and "Die 4". So ODT/CKE/NCS0 and
ODT/CKE/NCS1 must be connected to a single U340x.
Oh I thought U3401 would be "Die 1" and "Die 3" for chips connected to cs0.
Yeah probably you're right and U3401 is "Die 1" and "Die 2", otherwise
the ddr3 package would not even need separate balls for cke0 and cke1.

Cutting either would IMHO make half of the memory capacity unaccessible.
That would not be good..
Indeed. What I am really worried about is that I can't find any bit of information
about the cka and ckb except that ckb is not used for LPDDR2...

Hm. I think there was an AN about DDR3 for OMAP5 which might have more
information. I have to dig it out.

Well, I found what I thought could be relevant, but it was section
"7.7 DDR3 Board Design and Layout Guidelines" in SWPS050I and covers
only general PCB layout guidelines.

It provides no information about cka vs. ckb and other signals or EMIF setup.

BR,
Nikolaus
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