Am 09.11.2016 um 15:23 schrieb Michael Mrozek <EvilDragon@openpandora.org>:
Am Wed, 9 Nov 2016 13:41:24 +0100 hat "H. Nikolaus Schaller"
<hns@goldelico.com> geschrieben:
Hi,That's something to check them.Well, the specs from TI are everything except "exact". So following
As far as I know, Nikolaus thoroughly rechecked all traces that
have to do with the power supply on the CPU board and made sure
they follow exactly TIs specs earlier this year, because my first
idea also were power supply issues.
them exactly is not possible...
Hm, in the document Matthijs mentioned, I often fine "must be", etc.
• Whenever possible
• Minimizing the separation distance
• as close as possible
it is recommended to consider
• must be as wide as possible
In no such case it is clear when it is "good enough".
I've asked Nikolaus a couple of days ago to make a package of theYes, I am in the middle of making them drawn a little nicer so that
current schematics, etc., as the one I have do not reflect all the
changes made since the last prototype run (AFAIK).
they are easier to read.
Great, thanks!The remote sensing of VDD_MPU allows palmas to compensate meanIndeed.
voltage drop, but it is not going to deal with transients. Even if
it could measure and compensate fast enough (it can't), the loop
inductance of the power distribution net would probably prevent it
from succeeding. (Such an aggressive control loop would also be
prone to instability.)
So that's probably where we need to take a closer look at.Dealing with transients is still the job of decoupling caps asI didn't find that one but swps050i.
usual. TI gives quite a bit of guidance on the power distribution
nets in general (sections 7.2.1-7.2.4, 7.3 of swps051k)
A quick google showed up this one:
http://software-dl.ti.com/secure/techdocs/swps051k/swps051k?__gda__=1479563482_c6490a4ce11281967f82bf396cc380b5
You just need to login with your TI account and tell them you don't
want to nuclear bomb Trump.
But your citations below seem to indicate that swps050 and 051 have the
same index.
I had studied that as well as some Palmas Layout guide. But this is
>2 years ago so that I don't remember all details and especially I
do not remember the reasons for all decisions.
and decoupling caps in particular (e.g. section 7.3.2-7.3.4).Yes, it is guidance but it is not very helpful in detail. Quite a lot
of sentences are "should be" or "as good as possible" or "example".
Or "calculate with your design tools". Unfortunately we do not have
the big budget we would need to have such tools (e.g. calculate
resistance or inductance from PCB layout data).
Not sure if there's a difference, but swps051k quite often has "must"
in their text, not should be or similar.
And we have quite strong space constraints so that not everything can
be copied from the EVM (e.g. placing decoupling capacitors on the
backside under the OMAP5) or guide lines (there isn't much space for
adding more VIAs or moving traces to optimal positions).
The backside is completely unpopulated right now, but we have 0,5mm
space between it and the case.
Should be enough for capacitors, so why, for example, couldn't we put
decoupling capacitors there?
1. we didn't know before :)
2. we might at some time want to make the pyra thinner without limitations by the CPU board
3. we need to redesign the whole board
(This is just an example though, because according to the Datasheet:
"2. Place Dcaps on “same-side” as component within their power plane
outline to minimize “decoupling loop inductance”.
Target distance to
power pin should be less than ~500mils depending upon PCB
This is one of these contradictions where we might have to trade off.
With a chip dimension of 17x17 mm this more or less means "on the same
side as the BGA balls and as close as possible to the edge of the chip").
It looks as we have that.
layout characteristics (plane's layer assignment and solid nature). Use
PI modeling CAD tool to verify minimum inductance for top vs
bottom-side placement."
So it's better to have the DCaps on the same side of the OMAP5 anyways.
Except for:
"Place Dcaps on “opposite-side” as component within their power plane
outline if “same-side” is not feasible or if distance to power pin is
greater than ~500mils for top-side location."
How many mils are we away from the power pin?
Looking at 7.2.2 of the document, it also seems VERY important to have
multiple vias (not one for multiple capacitors), etc.
If I understand correctly, what we need to check for are the IR drop and
capacitance-inductance loop requirements... I have no idea how these
can be checked though (I'm not really experienced here).
Is that something you simulate from the PCB design files?
Windows workstation, we can easily simulate this.
EAGLE is not capable of doing that. Well, we could write our own tools
to convert the XML PCB data into something a simulation tool can use. But
this takes quite some time to make it reliable.
And something we should also check:
"Use minimum 10mil trace width for all voltage and gnd planes
connections (i.e. Dcap pads, component power pins, etc.)."
The minimum width used for all GND and power wires is 0.2 mm - but there
is additional GND filling.
I.e. big GND/power-strips like this for VDD-MPU:
One quite weak thing I see now is that there is only a single VIA to connect this big
area running in some inner layer to the surface. The problem is the space in this area
is also heavily used for signal wiring:
Well it could be possible to squeeze in one or two more VIAs in there.
And we could use one of the 2 layers we had added for getting the layout done to
add another connection strip between Palmas and OMAP. This would reduce resistance
definitively to less than 50% of the current value.
That such things are not optimal here is the result of finishing the CPU design
in a hurry last year to get the layout done for the first attempt. And a second
hurry this year as well. We likely have suboptimal trace layout because there was
not enough time (and manpower) to think about and peer-review such details.
And to be fair to ourselves - we didn't know for sure that it could be a potential
source of a problem.
Improvements here would need a change in board design. I am not sure if this is
within financial and time budgets.
And it could be a solution but as well it could remain unsolved if it is not
the problem.
"Use a “Power/Gnd pad/pin to via” ratio of 1:1 whenever possible. Do not
exceed 2:1 ratio for small number of vias within restricted PCB areas
(i.e. underneath BGA components)."
So it contains a lot of experience and is a big compromise - but
certainly not an optimal one.
I also think we're not that far off!
Maybe just a change in the decoupling capacitors could fix things...
"7.3.2 Voltage Decoupling" of the file is interesting here.
The recommend various decoupling capacitors, so we might have some ways
to play around here.
And capacitors can be changed without changing the board design.
"For power IC which can support more than 10uF close to processor, a
bulk capacitor of at least 22uF is strongly recommended for VDD_MPU
power domains."
Do we have that? :)
1. we did have 3x10µF at the Palmas side (measured as 22µF)
2. now we have 3x10µF at the Palmas side and 10µF at the OMAP side (measured as 34µF)
Seems to be 20% below. Or my capacitance measurements is imprecise.
So we have already increased the capacitors by ~50% with no significant
success @ 1.5GHz.
I have picked up some unpopulated CPU PCBs this morning and I can try
to measure resistances. If they are in the mOhm range (which is to be
expected) the precision might not be good.
Okay!
* Palmas A33 (SMPS3 feedback) *is* cut open in the new boards
* VDD-MPU and GND resistance between Palmas and OMAP is <0.3 Ohm
(my Multimeters are not more precise)
* my Smart Tweezers say 69 mOhm between one decoupling capacitor
and VDD-MPU but short circuit shows a bias of 43mOhm.
So I have to set up a precise bridge first and have to avoid thermo-
couple voltages. The most precise would probably to use pogo pins or
needles to contact the PCB.
BR,
Nikolaus